1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular, to a static type semiconductor memory device in which a memory cell has a flip-flop configuration. Specifically, the present invention relates to a layout of memory cells for reducing the power dissipation of the static type semiconductor memory devices.
2. Description of the Background Art
Semiconductor integrated circuit devices of high performance, such as system LSI's (large scale integrated circuits) or systems on chips (SOC), have been implemented with development of miniaturization technology. In such semiconductor integrated circuit devices, a logic circuit for executing a process, such as a processor, and a memory for storing data and program information used by the logic circuit are integrated on the same semiconductor chip. Such large scale integrated circuit devices are used in image processing, communication processing and others. In image processing and communication processing, it is required to process a large amount of data at high speed, and a memory that is assembled in the integrated circuit device is required to have an increased memory capacity.
In the case where the memory capacity of a memory (semiconductor memory device) is increased, it is required to arrange memory cells with high density without increasing the chip layout area, in view of suppressing an increase in cost, compatibility with devices of the previous generation and others. A structure in which substrate regions (well regions) for placing memory cell transistors are arranged extending linearly in column direction and the diffusion regions of the memory cells are formed into a linear, rectangular form, in order to arrange memory cells with high density is disclosed in Document 1 (Japanese Patent Laying-Open No. 2002-043441), Document 2 (Japanese Patent Laying-Open No. 2003-297953), Document 3 (Japanese Patent Laying-Open No. 2003-060089) and Document 4 (Japanese Patent Laying-Open No. 2001-028401).
In the layout of the memory cells shown in these Documents 1 to 4, access transistors and driver transistors which are formed of n channel MOS transistors (insulating gate type field effect transistors) are placed within P wells, and load transistors which are formed of p channel MOS transistors are placed within N wells which are formed adjacent to these P wells. Bit lines, power supply lines and ground lines are provided parallel to well regions in the column direction, and the power supply lines and the ground lines are connected to the source nodes of the load transistors and the source nodes of the driver transistors, respectively, in corresponding columns of memory cells. These references aim to simplify the interconnection layout and enable miniaturization of transistors by making the well regions extend linearly, and further to reduce the gate length of the transistors or the distance between the access transistors of the memory cells and the bit lines for reducing the interconnection resistance.
Where a memory device having a large memory capacity is implemented, it is required for the consumed power to be suppressed as much as possible, in terms of heat generation, battery life (in the case of application in portable equipments), and others. A configuration intending to reduce the current dissipation at standby and in operation is disclosed in Reference 1 (Technical Report of the Institute of Electronics, Information and Communication Engineers of Japan, Vol. 104, No. 66, “Development of Dual Port SRAM for SoC Using 90 nm Technology achieving Increase in Integration and Reduction in Power,” Nii et al.) and Reference 2 (ISSCC2004, Digest of Technical Papers “A 90 nm Dual-Port SRAM with 2.04 μm2 8T-Thin Cell Using Dynamically-Controlled Column Bias Scheme,” Nii et al.).
These References 1 and 2 disclose the same technical content: the voltage of the source line (ground line) that is connected to the driver transistors in a memory cell column unit is controlled for each column in a dual port SRAM. Specifically, the source voltage VSL of the driver transistors in unselected columns of memory cells is set at, for example, 0.4 V at a higher voltage level, while the source voltage of the driver transistors of memory cells in the selected column is driven to a ground voltage level. The gate to source bias of the driver transistors in the unselected memory cells is set into a reversed bias state, to make the driver transistor to be a deeper off state, so that the sub-threshold leakage current and the gate leakage current are reduced, and accordingly, the consumed current at standby is reduced.
The source line of the driver transistors is at the ground voltage level in the memory cell in the selected column and row, and in readout, the potential of the bit line is discharged in accordance with the stored data. In the memory cells in the selected column and unselected rows, only a leakage current which is smaller than the column current flows, and substantially negligible, as compared to the operation current. Furthermore, in the memory cells in the selected row and unselected columns, the driver transistor has the voltage between the gate and the source set to a reversed bias state, so that the bit lines are subject to substantially no discharging, the column current is suppressed and the consumed current in operation is reduced.
In the interconnection layout in the configuration shown in Documents 1, 2 and 4, power supply lines are placed in the center portion of memory cell regions, and ground lines are placed outside bit lines. Accordingly, ground lines are shared by memory cells in adjacent columns, and thus, the ground voltage cannot be controlled in units of columns, and the configuration in the above described References 1 and 2, in which the standby current and the operation current are reduced, cannot be applied.
In Document 3, FIG. 7 shows an interconnection layout where a ground line is placed in the center portion of memory cell and power supply line is placed outside bit lines. In this interconnection layout, ground lines is laced for each column, and thus, it is possible to adjust the potential of the ground lines for each column. However, in P well which is placed in the center portion of memory cell, an active region for forming two access transistors and two driver transistors is formed in rectangular form extending in the column direction. Four transistors are placed to be aligned in the column within the active region. Although the gates of these transistors extend in the row direction to simplify the interconnection layout, the pitch of memory cells in the column direction becomes the pitch of four transistors, and such a problem arises that the size of the memory cells in the column direction is large, as compared to a memory cell layout in which a pair of load transistors are placed in the center portion of memory cell region.
In addition, in the above described References 1 and 2, a ground line is placed between a pair of bit lines for each port, and a power supply line is placed between bit lines for different ports in a dual port SRAM. Accordingly, it becomes possible to use power supply lines and ground lines as shielding layers for bit lines, and the voltage level of ground lines can be adjusted for each column. In this configuration, however, load transistors are placed in N well in the center portion of memory cell region, and in the P wells on both sides, a pair of access transistors for the same port and one driver transistor are placed for each port, and a pair of bit lines for different ports are placed opposing to each other with respect to the center portion. Accordingly, the ground lines are arranged utilizing the memory cell configuration in the dual port SRAM, and thus, the arrangement of the ground lines in References 1 and 2 cannot be used simply directly in a single port SRAM.
It is frequently required to make simultaneous access via two ports for performing processes in an SOC or the like oriented to image processing and communication processing, and such parallel processing can be achieved using a dual port SRAM memory as described above. At present, however, a single port SRAM is generally used in an application such as a cache memory, and thus, a configuration where the potential of the source lines of the driver transistors for each column can be controlled without increasing the size of memory cells is also required in single port SRAM's. References 1 and 2 only discussed dual port SRAM's, and does not discuss single port SRAM's.